Method to reduce full-chip timing violation through time budgeting in integrated circuit design

Abstract

A method of time budgeting an integrated circuit (IC) that includes determining an initial value of time delay variables for each block of a plurality of blocks along a set of timing paths based on delays of each design module of the blocks and determining a value of at least one advanced timing factor adjusting a clock period of the IC along each timing path. The method then generates a time budget for ports along each timing path based on the value of the at least one advanced timing factor and the initial value of the time delay variable. The method then optimizes the value of time delay variables by calculating new values of the time delay variables that satisfy each timing path to minimize a possibility of timing violations and to satisfy the clock period of the IC, which is adjusted by the value of the advanced timing factor.