The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
Jun. 21, 2019
Applicant:
Empire Technology Development Llc, Wilmington, DE (US);
Inventor:
Yan Solihin, Raleigh, NC (US);
Assignee:
Empire Technology Development LLC, Wilmington, DE (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0842 (2016.01); G06F 1/32 (2019.01); G06F 12/126 (2016.01); G06F 15/173 (2006.01); G06F 12/0875 (2016.01); G06F 12/0846 (2016.01); G06F 12/128 (2016.01); G06F 15/78 (2006.01); G06F 9/50 (2006.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0842 (2013.01); G06F 1/32 (2013.01); G06F 12/08 (2013.01); G06F 12/0848 (2013.01); G06F 12/0875 (2013.01); G06F 12/126 (2013.01); G06F 12/128 (2013.01); G06F 15/17381 (2013.01); G06F 15/781 (2013.01); G06F 9/5077 (2013.01); G06F 12/12 (2013.01); G06F 2212/282 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6012 (2013.01); Y02D 10/00 (2018.01);
Abstract
Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.