Semiconductor memory devices, and methods of operating semiconductor memory devices

Abstract

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a data region and a parity region. The I/O gating circuit is connected to the ECC engine and the memory cell array. The control logic circuit generates control signals by decoding a command received from a memory controller. The ECC engine is configured to a first parity data based on a first write data associated with a first command. The control logic circuit is further configured to adjust a first write timing to write the first parity data in the parity region based on a receiving timing of a second command successive to the first command and a reference time interval.