The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Dec. 15, 2015
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Andreas Hansson, Cambridge, GB;

Ian Rudolf Bratt, Portola Valley, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 13/16 (2013.01); G06F 13/1631 (2013.01); G06F 12/12 (2013.01); G06F 2212/221 (2013.01);
Abstract

An apparatus and method are provided for issuing access requests to a memory controller for a memory device whose memory structure consists of a plurality of sub-structures. The apparatus has a request interface for issuing access requests to the memory controller, each access request identifying a memory address. Within the apparatus static abstraction data is stored providing an indication of one or more of the sub-structures of the memory device, and the apparatus also stores an indication of outstanding access requests issued from the request interface. Next access request selection circuitry is then arranged to select from a plurality of candidate access requests a next access request to issue from the request interface. That selection is dependent on sub-structure indication data that is derived from application of an abstraction data function, using the static abstraction data, to the memory addresses of the candidate access requests and the outstanding access requests. Such an approach enables the apparatus to provide a series of access requests to the memory controller with the aim of enabling the memory controller to perform a more optimal access sequence with regard to the memory device.


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