The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

May. 21, 2019
Applicant:

Nxp B.v., Eindhoven, NL;

Inventor:

Antoine Fabien Dubois, San Jose, CA (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/165 (2006.01); H03K 17/687 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
G01R 19/16519 (2013.01); H03K 17/687 (2013.01); H03M 1/12 (2013.01);
Abstract

A system includes a power transistor having a first drain connected to a load, a first gate connected to a gate driver, wherein the gate driver is configured to drive a first gate voltage on the first gate, and a first source connected to a ground. A sampling transistor includes a second drain connected to the first gate, a second gate connected to the first drain and a second source. A sampling capacitor is connected between the second source and the ground, wherein the sampling transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor, in response to the first gate voltage increasing to the Miller plateau voltage and a first drain voltage of the first drain decreasing to a value equal to the Miller plateau voltage plus a threshold voltage of the sampling transistor.


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Dubois, Antoine. (2021). Automatic miller plateau sampling (U.S. Patent No. 10955445). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10955445

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