The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Jun. 27, 2019
Applicant:

Dura Operating, Llc, Auburn Hills, MI (US);

Inventors:

Ron G. Gipson, Metamora, MI (US);

Bhanumurthy Veeragandham, Auburn Hills, MI (US);

Indraneel Page, Farmington Hills, MI (US);

Assignee:

DUS OPERATING INC., Auburn Hills, MI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/14 (2006.01); H05K 1/18 (2006.01); H05K 3/36 (2006.01); F21V 7/00 (2006.01); F21V 7/04 (2006.01); G02F 1/133 (2006.01); G02F 1/1333 (2006.01); G02F 1/1335 (2006.01); H05K 1/02 (2006.01); H05K 7/14 (2006.01); H05K 3/28 (2006.01); B62D 25/04 (2006.01); H05K 3/34 (2006.01); F21Y 115/10 (2016.01);
U.S. Cl.
CPC ...
H05K 1/14 (2013.01); B62D 25/04 (2013.01); F21V 7/0066 (2013.01); H05K 1/0277 (2013.01); H05K 1/181 (2013.01); H05K 3/284 (2013.01); H05K 3/341 (2013.01); H05K 3/36 (2013.01); H05K 7/1427 (2013.01); F21Y 2115/10 (2016.08); H05K 2201/10113 (2013.01); H05K 2201/10356 (2013.01);
Abstract

An electronic assembly and a method of forming an electronic assembly. The electronic assembly including a printed circuit board including a first face, a flexible printed circuit connected to the first face of the printed circuit board, a filler component arranged over a first portion of the first face of the printed circuit board, a housing defining a cavity, wherein the filler component is arranged in the cavity, a channel guide extending from the housing, wherein the flexible printed circuit sits in the channel guide, and a substrate positioned adjacent to a second face of the printed circuit board, wherein the second face opposes the first face.


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