The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Jul. 18, 2018
Applicant:

No.24 Research Institute of China Electronics Technology Group Corporation, Chongqing, CN;

Inventors:

Yong Zhang, Chongqing, CN;

Ting Li, Chongqing, CN;

Zhengbo Huang, Chongqing, CN;

Yabo Ni, Chongqing, CN;

Dongbing Fu, Chongqing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1009 (2013.01); H03M 1/0612 (2013.01); H03M 1/0641 (2013.01);
Abstract

The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain. In the present disclosure, a capacitor voltage coefficient can be extracted based on INL and the capacitor voltage coefficient is calibrated at a digital backend without adding an analog calibration circuit, thereby improving conversion accuracy of the ADC.


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