The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Feb. 25, 2020
Applicant:

Inphi Corporation, Santa Clara, CA (US);

Inventors:

Xiaoguang He, Diamond Bar, CA (US);

Radhakrishnan L. Nagarajan, Santa Clara, CA (US);

Assignee:

INPHI CORPORATION, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/00 (2013.01); H01S 5/00 (2006.01); H01S 5/022 (2021.01); H01S 5/02 (2006.01); H01S 5/323 (2006.01); H04B 10/27 (2013.01); H04B 10/07 (2013.01); G01R 31/26 (2020.01); G02B 6/12 (2006.01); H01S 5/12 (2021.01);
U.S. Cl.
CPC ...
H01S 5/0042 (2013.01); G01R 31/2635 (2013.01); G02B 6/12004 (2013.01); H01S 5/021 (2013.01); H01S 5/0224 (2013.01); H01S 5/323 (2013.01); H04B 10/07 (2013.01); H04B 10/27 (2013.01); H01S 5/12 (2013.01);
Abstract

A light source based on integrated silicon photonics includes a die of a silicon substrate having at least one chip site configured with a surface region, a trench region, and a first stopper region located separately between the surface region and the trench region. The trench region is configured to be a depth lower than the surface region. The light source includes a laser diode chip having a p-side facing the chip site and a n-side being distal to the chip site. The p-side includes a gain region bonded to the trench region, an electrode region bonded to the surface region, and an isolation region engaged with the stopper region to isolate the gain region from the electrode region. The light source also includes a conductor layer in the die configured to connect the gain region to an anode electrode and separately connect the electrode region to a cathode electrode.


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