The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Jul. 01, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jeonghyuk Yim, Seoul, KR;

Wandon Kim, Seongnam-si, KR;

Weonhong Kim, Suwon-si, KR;

Jongho Park, Suwon-si, KR;

Hyeonjun Baek, Hwaseong-si, KR;

Byounghoon Lee, Suwon-si, KR;

Sangjin Hyun, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 21/28088 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/4966 (2013.01); H01L 29/6684 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.


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