The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Dec. 05, 2017
Applicants:

Institut Vedecom, Versailles, FR;

Elvia Pcb, Coutances, FR;

Inventors:

Friedbald Kiel, Fontainebleau, FR;

Olivier Belnoue, Ondreville-sur-Essonne, FR;

Assignees:

INSTITUT VEDECOM, Versailles, FR;

ELVIA PCB, Coutances, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/488 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/367 (2013.01); H01L 23/3735 (2013.01); H01L 23/488 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01);
Abstract

The method comprises the steps of 1) producing first and second blanks (EB, EB) by laminating insulating and conductive inner layers (PP, CP, E) on copper plates forming a base (MB, MB), at least one electronic chip (MT, MD) being sandwiched between the blanks, said blanks being produced such that their upper lamination surfaces have matching profiles, 2) stacking and fitting the blanks via their matching profiles, and 3) press-fitting the blanks to form a laminated sub-assembly for an integrated power electronics device. The method uses IMS-type techniques.


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