The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2021

Filed:

Dec. 11, 2019
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

SeyedMohammad SeyedzadehDelcheh, Bellevue, WA (US);

Steven Raasch, Boxborough, MA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4078 (2006.01); G11C 11/406 (2006.01); G06F 12/1018 (2016.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4078 (2013.01); G06F 12/1018 (2013.01); G11C 11/4085 (2013.01); G11C 11/40607 (2013.01); G11C 11/40615 (2013.01); G11C 11/40618 (2013.01);
Abstract

An integrated circuit includes an aggressor wordline cache and logic that determines a candidate upper adjacent address and a candidate lower adjacent address of a target memory row corresponding to a read request to memory. When at least one of the candidate upper adjacent address or the candidate lower adjacent address are determined to be a victim row, the logic checks the aggressor wordline cache for a cache hit for the target memory row. When there is a cache hit in the aggressor wordline cache, the logic sends a corresponding cache line as a response to the read request, otherwise the logic causes a read of content from the memory. In certain examples, the logic includes a stored bit array and a hash function-based filter, which determines whether any of the candidate upper adjacent address and the candidate lower adjacent address are victim rows represented in the stored bit array.


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