The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2021
Filed:
Oct. 09, 2019
Applicant:
Western Digital Technologies, Inc., San Jose, CA (US);
Inventors:
Darin Edward Gerhart, Oronoco, MN (US);
Nicholas Edward Ortmeier, Rochester, MN (US);
Mark David Erickson, Mantorville, MN (US);
Assignee:
WESTERN DIGITAL TECHNOLOGIES, INC., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0879 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0632 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 12/0879 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/60 (2013.01);
Abstract
A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.