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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10947109 B1

PDFFull Text
Date of Patent:
Mar. 16, 2021

Filed:

Sep. 26, 2018

Semiconductor component and method for producing same

Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Mathias Vaupel, Regensburg, DE;

Bernhard Knott, Neumarkt, DE;

Horst Theuss, Wenzenbach, DE;

Assignee:

Infineon Technologies AG;

Attorney:

Design IP

Primary Examiner:

Brook Kebede

Int. Cl.
CPC ...
H01L 29/84 (2006.01); B81B 7/00 (2006.01); H01L 23/04 (2006.01); H01L 23/24 (2006.01); H01L 23/498 (2006.01); H01L 23/16 (2006.01); B81C 1/00 (2006.01); H01L 21/311 (2006.01); H01L 21/52 (2006.01); H01L 21/56 (2006.01); H01L 23/055 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
B81B 7/0058 (2013.01); B81C 1/00301 (2013.01); H01L 21/31144 (2013.01); H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 23/04 (2013.01); H01L 23/055 (2013.01); H01L 23/16 (2013.01); H01L 23/24 (2013.01); H01L 23/3121 (2013.01); H01L 23/49541 (2013.01); H01L 23/49861 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); B81B 2201/0264 (2013.01); H01L 23/49551 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01);
Abstract

A method for producing a semiconductor component is proposed. The method includes providing a housing. At least one semiconductor chip is arranged in a cavity of the housing. Furthermore, an electrical contact of the semiconductor chip is connected to an electrical contact of the housing via a bond wire. The method furthermore includes applying a protective material on the electrical contact of the semiconductor chip and also on a region of the bond wire which is adjacent to the electrical contact of the semiconductor chip, and/or on the electrical contact of the housing and also on a region of the bond wire which is adjacent to the electrical contact of the housing. Moreover, the method also includes filling at least one partial region of the cavity with a gel.

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