Asynchronous clock gating cells and related methods to provide a gated clock output

Abstract

Improved clock gating cells and related methods are provided. The clock gating cells include a first mutually exclusive element (ME), a first inverter and a second mutually exclusive element (ME). MEreceives a clock input and an enable signal, which is asynchronous to the clock input, and outputs the enable signal based on a timing relationship between the clock input and the enable signal. The first inverter receives the enable signal output from MEand provides an inverted enable signal to ME. MEreceives the clock input and the inverted enable signal, and provides a clock output based on a timing relationship between the clock input and the inverted enable signal. Together, MEand MEresolve meta-stability and eliminate glitches in the clock output by preventing rising and falling edges of the enable signal from passing through the mutually exclusive elements during active phases of the clock input.