The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Jun. 05, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Subbarao Surendra Chakkirala, San Jose, CA (US);

Sherif Galal, Irvine, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/13 (2014.01); H03K 5/00 (2006.01); H03K 19/20 (2006.01); H03K 3/037 (2006.01); G06F 1/08 (2006.01); H03F 3/217 (2006.01);
U.S. Cl.
CPC ...
H03K 5/00 (2013.01); G06F 1/08 (2013.01); H03F 3/217 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01); H03K 2005/00078 (2013.01);
Abstract

In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.


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