The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Oct. 30, 2018
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Nadim Khlat, Cugnaux, FR;

James M. Retz, Cedar Rapids, IA (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/32 (2006.01); H03F 1/02 (2006.01); H03F 3/19 (2006.01); H03G 3/30 (2006.01); H04B 1/04 (2006.01);
U.S. Cl.
CPC ...
H03F 1/3241 (2013.01); H03F 1/02 (2013.01); H03F 3/19 (2013.01); H03G 3/3036 (2013.01); H03G 3/3089 (2013.01); H04B 1/04 (2013.01); H03F 2200/102 (2013.01); H03F 2200/451 (2013.01); H03F 2201/3215 (2013.01); H03G 2201/103 (2013.01); H03G 2201/307 (2013.01); H04B 2001/045 (2013.01); H04B 2001/0416 (2013.01); H04B 2001/0425 (2013.01);
Abstract

An envelope tracking (ET) amplifier circuit is provided. The ET amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET modulated voltage. The ET modulated voltage corresponds to a time-variant voltage envelope, which can be misaligned from a time-variant signal envelope of the RF signal due to inherent temporal delay in the ET amplifier circuit. As a result, the amplifier circuit may suffer degraded linearity performance. In this regard, a voltage processing circuit is provided in the ET amplifier circuit and configured to operate in a low-bandwidth mode and a high-bandwidth mode. In the high-bandwidth mode, the voltage processing circuit is configured to cause the ET modulated voltage to be modified to help improve delay tolerance of the ET amplifier circuit. As a result, it may be possible to reduce linearity degradation of the amplifier circuit to a predetermined threshold.


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