The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2021
Filed:
Jan. 24, 2020
Applicant:
Sumitomo Electric Industries, Ltd., Osaka, JP;
Inventor:
Ken Nakata, Osaka, JP;
Assignee:
SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/316 (2006.01); H01L 29/778 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 21/465 (2006.01); H01L 21/443 (2006.01); H01L 21/027 (2006.01); H01L 29/267 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/786 (2006.01); H01L 21/8234 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0254 (2013.01); H01L 21/02057 (2013.01); H01L 21/0262 (2013.01); H01L 21/0273 (2013.01); H01L 21/02178 (2013.01); H01L 21/02189 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02576 (2013.01); H01L 21/02631 (2013.01); H01L 21/02636 (2013.01); H01L 21/30621 (2013.01); H01L 21/443 (2013.01); H01L 21/465 (2013.01); H01L 29/0891 (2013.01); H01L 29/1029 (2013.01); H01L 29/267 (2013.01); H01L 29/66462 (2013.01); H01L 29/66969 (2013.01); H01L 29/7786 (2013.01); H01L 21/02458 (2013.01); H01L 21/02502 (2013.01); H01L 21/823418 (2013.01); H01L 29/0843 (2013.01); H01L 29/2003 (2013.01); H01L 29/45 (2013.01); H01L 29/66636 (2013.01); H01L 29/78681 (2013.01);
Abstract
A process of forming a field transistor (FET) and a FET are disclosed. The FET includes a nitride semiconductor stack on a substrate. A pair of n-regions made of oxide semiconductor material are provided within respective recesses in the semiconductor stack. Protecting layers, each made of oxide material, cover peripheries of the n-regions. Electrodes are provided in openings in the protecting layers to be in direct contact with the n-regions.