The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Aug. 12, 2019
Applicant:

Allegro Microsystems, Llc, Manchester, NH (US);

Inventors:

Sundar Chetlur, Bedford, NH (US);

Maxim Klebanov, Manchester, NH (US);

Washington Lamar, Mont Vernon, NH (US);

Assignee:

Allegro MicroSystems, LLC, Manchester, NH (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/06 (2006.01); H01L 27/02 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 27/027 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/0688 (2013.01); H01L 29/4236 (2013.01); H01L 29/518 (2013.01); H01L 29/7827 (2013.01); H01L 21/823412 (2013.01); H01L 21/823487 (2013.01);
Abstract

A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.


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