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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10943856 B1

PDFFull Text
Date of Patent:
Mar. 09, 2021

Filed:

Jul. 02, 2019

System in package device including inductor

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Yien Sien Khoo, Melaka, MY;

Siew Kee Lee, Kedah, MY;

Assignee:

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);

Attorneys:

Dawn Jos

Charles A. Brill

Frank D. Cimino

Primary Examiner:

Ida M Soward

Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 23/31 (2006.01); H01F 1/14 (2006.01); H01F 1/36 (2006.01); H01L 23/495 (2006.01); H01F 27/02 (2006.01); H01F 27/29 (2006.01); H01L 21/48 (2006.01); H01L 49/02 (2006.01); H01L 21/56 (2006.01); H01F 27/255 (2006.01); H01F 1/147 (2006.01); H02M 3/158 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49541 (2013.01); H01F 1/14766 (2013.01); H01F 1/36 (2013.01); H01F 27/027 (2013.01); H01F 27/255 (2013.01); H01F 27/29 (2013.01); H01F 27/292 (2013.01); H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/495 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49537 (2013.01); H01L 28/10 (2013.01); H01F 2027/295 (2013.01); H01L 23/3107 (2013.01); H01L 23/49575 (2013.01); H01L 23/645 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/19042 (2013.01); H02M 3/158 (2013.01);
Abstract

Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 μms.

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