The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Aug. 22, 2019
Applicant:

Elpis Technologies Inc., Ottawa, CA;

Inventors:

Qing Cao, Yorktown Heights, NY (US);

Shu-Jen Han, Cartlandt Manor, NY (US);

Ning Li, White Plains, NY (US);

Jianshi Tang, Elmsford, NY (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/265 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 21/3205 (2006.01); B82Y 10/00 (2011.01); H01L 29/40 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2807 (2013.01); B82Y 10/00 (2013.01); H01L 21/26513 (2013.01); H01L 21/28088 (2013.01); H01L 21/32056 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66568 (2013.01); H01L 29/78 (2013.01); H01L 29/0673 (2013.01); H01L 29/775 (2013.01);
Abstract

A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.


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