The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Aug. 29, 2019
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Lalit Gupta, Cupertino, CA (US);

Shri Sagar Dwivedi, San Jose, CA (US);

Fakhruddin Ali Bohra, San Jose, CA (US);

Gaurav Rattan Singla, San Jose, CA (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/14 (2006.01); G11C 5/06 (2006.01); G11C 8/14 (2006.01); G11C 29/00 (2006.01); G11C 11/4091 (2006.01); G11C 8/18 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 29/76 (2013.01); G11C 5/06 (2013.01); G11C 7/14 (2013.01); G11C 8/14 (2013.01); G11C 8/18 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/4091 (2013.01);
Abstract

Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.


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