The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Mar. 31, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

James Mac Freitag, Sunnyvale, CA (US);

Zheng Gao, San Jose, CA (US);

Susumu Okamura, Fujisawa, JP;

Yongchul Ahn, San Jose, CA (US);

Aron Pentek, San Jose, CA (US);

Amanda Baer, Campbell, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/235 (2006.01); G11B 5/31 (2006.01); G11B 5/127 (2006.01); G11B 5/39 (2006.01); G11B 5/02 (2006.01); G11B 5/00 (2006.01); G11B 5/23 (2006.01);
U.S. Cl.
CPC ...
G11B 5/3146 (2013.01); G11B 5/1278 (2013.01); G11B 5/235 (2013.01); G11B 5/314 (2013.01); G11B 5/3116 (2013.01); G11B 5/02 (2013.01); G11B 5/232 (2013.01); G11B 5/315 (2013.01); G11B 5/3153 (2013.01); G11B 5/3983 (2013.01); G11B 2005/0024 (2013.01);
Abstract

In one embodiment, a write head includes a spin polarization layer (SPL) over a seed layer. A spacer layer is over the SPL. A trailing shield is over the spacer layer. The spacer layer forms a first interface between the spacer layer and the trailing shield and forms a second interface between the spacer layer and the SPL. The first interface has an area larger than an area of the second interface. In another embodiment, a write head includes a SPL over a spacer layer. A capping layer is over the SPL. A trailing shield is over the capping layer. The spacer layer forms a first interface between the spacer layer and the main pole and forms a second interface between the spacer layer and the SPL. The first interface has an area larger than an area of the second interface.


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