The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2021
Filed:
Mar. 26, 2020
Xilinx, Inc., San Jose, CA (US);
Jichun Wang, San Jose, CA (US);
Chun Zhang, San Jose, CA (US);
Fan Zhang, San Jose, CA (US);
Bing Tian, San Jose, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Examples described herein provide a method for optimizing a netlist for an integrated circuit device. The method generally includes receiving a netlist comprising a first lookup table, and upstream logic, wherein the upstream logic receives a plurality of input signals and comprises at least one output connected as at least one input to the first lookup table, wherein the first lookup table comprises an unused input and multiple outputs; mapping the plurality of input signals directly to the at least one input and the unused input of the first lookup table; validating the mapping by monitoring the multiple outputs of the first lookup table; and upon a successful validation, optimizing the netlist by removing the upstream logic and reconnecting the plurality of input signals to the at least one input and the unused input of the first lookup table.