The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Feb. 14, 2019
Applicant:

Massachusetts Institute of Technology, Cambridge, MA (US);

Inventor:

Andrew J. Kerman, Arlington, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06Q 10/00 (2012.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06Q 10/00 (2013.01);
Abstract

A device combines physical qubits into a logical qubit according to a passive, quantum error-suppressing code, and weaves logical qubits into a fabric for performing computation or annealing according to an active, quantum error-correcting code. By using enough physical qubits in each logical qubit, the error suppression can overcome errors introduced by ambient noise, such as thermal fluctuations. However, interactions between individual logical qubits are based on interactions between multiple physical qubits, such as XX or ZZ interactions, so logical interactions require intermediary circuitry capable of coupling four or more spins-this circuitry also is described, wherein coupling an ancilla qubit to such intermediary circuitry allows the formation of a logical qubit having passive error suppression, and arbitrary computations can be performed using a fabric of such circuitry. Concatenating the active and passive codes does not increase circuit complexity, or reduce the speed of gate operations.


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