The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Oct. 17, 2019
Applicant:

Phison Electronics Corp., Miaoli, TW;

Inventor:

Ming-Chien Huang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/06 (2006.01); H04L 7/033 (2006.01); G11C 8/18 (2006.01); G11C 11/4076 (2006.01); G06F 1/08 (2006.01); H03K 5/135 (2006.01); H03L 7/085 (2006.01); G11C 29/02 (2006.01); G11C 7/22 (2006.01); H03L 7/00 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); H03K 5/135 (2013.01); H03L 7/085 (2013.01); G06F 1/06 (2013.01); G06F 13/16 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 8/18 (2013.01); G11C 11/4076 (2013.01); G11C 29/023 (2013.01); H03L 7/00 (2013.01); H04L 7/033 (2013.01); H04L 7/0331 (2013.01);
Abstract

A connection interface circuit, a memory storage device and a signal generation method are disclosed. The connection interface circuit is configured to connect a memory controller to a volatile memory module. The connection interface circuit includes a phase locking circuit, a wire module and a signal interface. The signal interface is coupled between the wire module and the memory controller. The phase locking circuit is configured to receive a first clock signal from the memory controller. The phase locking circuit is further configured to generate a second clock signal according to the first clock signal and a delay feature of the wire module. The wire module is configured to provide a third clock signal to the signal interface according to the second clock signal.


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