The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Mar. 05, 2020
Applicants:

Stmicroelectronics (Grenoble 2) Sas, Grenoble, FR;

Stmicroelectronics Asia Pacific Pte Ltd, Singapore, SG;

Inventors:

Lookah Chua, Singapore, SG;

Jansen Reyes Duey, Singapore, SG;

Tarek Lule, Saint-Egreve, FR;

Mathieu Thivin, Voreppe, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 17/00 (2006.01); H04N 5/369 (2011.01); H04N 5/3745 (2011.01); B60W 30/09 (2012.01); G08G 1/16 (2006.01);
U.S. Cl.
CPC ...
H04N 17/002 (2013.01); H04N 5/3696 (2013.01); H04N 5/37452 (2013.01); B60W 30/09 (2013.01); B60W 2420/42 (2013.01); G08G 1/167 (2013.01);
Abstract

An electronic device includes a voltage divider producing different reference voltages. Dummy pixels each are formed by a transfer gate transistor having a first conduction terminal coupled to a floating diffusion node, a second conduction terminal, and a control node coupled to a first gate signal line, a transmission gate coupled between one of the plurality of taps and the second conduction terminal of the transfer gate transistor, a floating diffusion capacitor coupled between the floating diffusion node and ground, a transistor having a first conduction terminal coupled to the floating diffusion node, a second conduction terminal, and a control terminal coupled to a second gate signal line, and a reset transistor having a first conduction terminal coupled to the upper reference voltage, a second conduction terminal coupled to the second conduction terminal of the transistor, and a control terminal coupled to a reset signal line.


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