The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Mar. 21, 2019
Applicants:

Samsung Electronics Co., Ltd., Suwon-si, KR;

University of Massachusetts, Boston, MA (US);

Inventors:

Byunghoon Na, Suwon-si, KR;

Mahdad Mansouree, Amherst, MA (US);

Seunghoon Han, Seoul, KR;

Amir Arbabi, Amherst, MA (US);

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/183 (2006.01); H01S 5/343 (2006.01); H01S 5/347 (2006.01); H01S 5/42 (2006.01); G01P 13/00 (2006.01); H01S 5/042 (2006.01); G01B 11/24 (2006.01); G01B 11/14 (2006.01);
U.S. Cl.
CPC ...
H01S 5/18361 (2013.01); G01B 11/14 (2013.01); G01B 11/24 (2013.01); G01P 13/00 (2013.01); H01S 5/0421 (2013.01); H01S 5/0425 (2013.01); H01S 5/343 (2013.01); H01S 5/347 (2013.01); H01S 5/423 (2013.01);
Abstract

Provided are an addressable laser array device and an electronic apparatus including the addressable laser array device. The addressable laser array device includes a plurality of VCSELs, each including a distributed Bragg reflector (DBR), a nanostructure reflector including a plurality of nanostructures having a sub-wavelength dimension, and a gain layer disposed between the DBR and the nanostructure reflector; a plurality of first wiring patterns extending in a first direction and being electrically connected to the plurality of VCSELs, respectively; and a plurality of second wiring patterns extending in a second direction intersecting the first direction and being electrically connected to the plurality of VCSELs, respectively, wherein the plurality of VCSELs are disposed at intersections of the plurality of first wiring patterns and the plurality of second wiring patterns, and the addressable VCSEL array device is configured to selectively drive at least some of the plurality of VCSELs.


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