The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Sep. 27, 2018
Applicant:

Sharp Kabushiki Kaisha, Osaka, JP;

Inventor:

Hiroshi Matsukizono, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/32 (2006.01); H01L 29/786 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1218 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1251 (2013.01); H01L 27/1285 (2013.01); G02F 1/1368 (2013.01); H01L 27/3244 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01);
Abstract

An active matrix substrate () according to an embodiment of the present invention has a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix pattern, and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (), a first TFT () supported on the substrate and including a crystalline silicon semiconductor layer (), and a second TFT () supported on the substrate and including an oxide semiconductor layer (). The first TFT and the second TFT each have a top gate structure. The oxide semiconductor layer is located below the crystalline silicon semiconductor layer.


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