The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Mar. 04, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Shinichi Nakao, Yokkaichi, JP;

Kei Watanabe, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11521 (2017.01); H01L 27/1156 (2017.01); H01L 27/11519 (2017.01); H01L 21/28 (2006.01); H01L 27/11556 (2017.01); H01L 21/02 (2006.01); H01L 27/11565 (2017.01); H01L 29/40 (2006.01); H01L 23/00 (2006.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0223 (2013.01); H01L 23/562 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 29/408 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08);
Abstract

In one embodiment, a semiconductor device includes electrode layers and insulating layers alternately provided on a substrate and stacked in a first direction perpendicular to a surface of the substrate, and semiconductor layers provided in the electrode layers and insulating layers, extending in the first direction, and adjacent to each other in a second direction parallel to the surface of the substrate. The device further includes first and second charge trapping layers provided between the semiconductor layers and electrode layers sandwiching the semiconductor layers in a third direction parallel to the surface of the substrate. The device further includes insulators provided between the semiconductor layers being adjacent to each other in the second direction, and including a first insulator having a first width, and a second insulator having a second width longer than the first width and having nitrogen concentration different from that in the first insulator.


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