The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Mar. 21, 2017
Applicant:

Inno-pach Technology Pte Ltd, Singapore, SG;

Inventors:

Wanning Zhang, Shanghai, CN;

Deze Yu, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 25/07 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/072 (2013.01); H01L 21/4853 (2013.01); H01L 21/4871 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 23/367 (2013.01); H01L 23/5381 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/96 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/214 (2013.01); H01L 2224/95001 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01);
Abstract

Disclosed herein are a chip packaging method and a device with packaged chips. The method includes: providing a support plate attached thereon with a first bonding layer; placing a plurality of chips onto the first bonding layer at intervals; performing a plastic packaging process to form a plastic packaging layer filling the gaps between the chips over the support plate, so that the plastic packaged chips are formed; removing the support plate and the first bonding layer to form the plastic packaged chips; forming an insulating layer over the plastic packaged chips, forming openings in the insulating layer and depositing metal in the openings to form a metal conducting layer and an interconnect circuitry; dicing the plastic packaged chips into a plurality of modules. The method reduces the distances between the chips, reduces the size of terminal products, and facilitates the miniaturization of the terminal products.


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