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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10937765 B1

PDFFull Text
Date of Patent:
Mar. 02, 2021

Filed:

Oct. 08, 2019

Semiconductor device with laminated semiconductor chips

Applicant:

Ultramemory Inc., Tokyo, JP;

Inventors:

Naoki Ogawa, Tokyo, JP;

Toshitugu Ueda, Tokyo, JP;

Kazuo Yamaguchi, Tokyo, JP;

Assignee:

ULTRAMEMORY INC., Tokyo, JP;

Attorney:

Muncy, Geissler, Olds & Lowe, P.C.

Primary Examiner:

Gene N Auduong

Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/48 (2006.01); H01L 25/07 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 27/108 (2006.01); H01L 25/18 (2006.01); H01L 49/02 (2006.01); H04B 5/00 (2006.01); H04B 5/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/48 (2013.01); H01L 23/498 (2013.01); H01L 23/645 (2013.01); H01L 25/065 (2013.01); H01L 25/07 (2013.01); H01L 25/18 (2013.01); H01L 27/108 (2013.01); H01L 28/10 (2013.01); H04B 5/0081 (2013.01); H04B 5/02 (2013.01);
Abstract

A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil. The semiconductor device is also provided with an interposer, which is disposed on one end in the laminating direction of the memory chips, and which has, for each of the memory chips: a second transmission/reception coil coupled to the first transmission/reception coil by means of inductive coupling; second lead-out lines led out from both ends of the second transmission/reception coil; and a second transmission/reception circuit, which is connected to the second lead-out lines, and which inputs/outputs signals to/from the second transmission/reception coil.

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