The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Nov. 06, 2019
Applicant:

Hrl Laboratories, Llc, Malibu, CA (US);

Inventors:

Danny M. Kim, Agoura Hills, CA (US);

Rongming Chu, Agoura Hills, CA (US);

Yu Cao, Agoura Hills, CA (US);

Thaddeus D. Ladd, Woodland Hills, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/20 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02603 (2013.01); H01L 21/0242 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02389 (2013.01); H01L 21/02488 (2013.01); H01L 21/02609 (2013.01); H01L 21/02639 (2013.01); H01L 29/0673 (2013.01); H01L 29/2003 (2013.01);
Abstract

Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.


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