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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10936774 B1

PDFFull Text
Date of Patent:
Mar. 02, 2021

Filed:

Feb. 14, 2019

Methods for identifying integrated circuit failures caused by reset-domain interactions

Applicants:

Oren Katzir, Sunnyvale, CA (US);

Real Intent, Inc., Sunnyvale, CA (US);

Inventors:

Oren Katzir, San Jose, CA (US);

Sanjeev Mahajan, Mountain View, CA (US);

Prakash Narain, San Carlos, CA (US);

Vishnu Vimjam, San Jose, CA (US);

Assignee:

Real Intent, Inc., Sunnyvale, CA (US);

Attorney:

Pranav Ashar

Primary Examiner:

Helen Rossoshek

Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/3323 (2020.01); G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 30/20 (2020.01); G06F 111/04 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/20 (2020.01); G06F 30/30 (2020.01); G06F 30/3323 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01);
Abstract

Integrated circuit failures caused by metastability related to assertion of asynchronous resets frequently escape detection before fabrication, causing design respins and severe economic loss. The numerous reset signals, flip-flops and complex logical interactions inherent in an integrated circuit cause an analysis for reset-metastability failures to be extremely noisy, reporting an unmanageable number of false failures and making early removal of failures impractical. Said noisy reporting arises because many flip-flops where reset-metastability manifests do not necessarily cause overall failure. An effective analysis of reset-metastability failures must identify all potential failures, but also must only report true failure potential. The present invention maximizes noise reduction by applying special conditions to identify flip-flops manifesting reset-metastability without causing integrated circuit failure, which can thereby be deemed safe. By reporting only true failure potential, the present invention enables efficient, robust and error-free removal of reset-related failures from an integrated circuit prior to fabrication.

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