The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Oct. 02, 2019
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventor:

Avdhesh Chhodavdia, Freemont, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/00 (2006.01); G06F 30/30 (2020.01); G06F 9/50 (2006.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/343 (2020.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 9/5011 (2013.01); G06F 9/5044 (2013.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/343 (2020.01);
Abstract

Systems and methods for using a common fuse controller hardware design for different applications are described. A method includes specifying a first fuse map for a first system on a chip (SoC) and a second fuse map for a second SoC. The method further includes processing the first fuse map to generate a first hardware description language (HDL) file and processing the second fuse map to generate a second HDL file. The method further includes using a processor, compiling a common hardware state machine HDL file with the first HDL file to generate a first output file capturing behavior expressed in the first fuse map or compiling the common hardware state machine HDL file with the second HDL file to generate a second output file capturing behavior expressed in the second fuse map.


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