The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Jun. 25, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Norbert Hagspiel, Tuebingen, DE;

Sascha Junghans, Ammerbuch, DE;

Matthias Klein, Wappingers Falls, NY (US);

Joerg Walter, Tuebingen, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/084 (2016.01); G06F 13/28 (2006.01); G06F 12/0811 (2016.01); G06F 12/0868 (2016.01); G06F 12/0871 (2016.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0868 (2013.01); G06F 12/0871 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/6042 (2013.01);
Abstract

A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.


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