The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Oct. 17, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Dietrich Bonart, Bad Abbach, DE;

Thomas Gross, Sinzing, DE;

Franziska Haering, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01); H01L 23/525 (2006.01); H01L 23/528 (2006.01); H01L 21/66 (2006.01); H01L 23/522 (2006.01); G01R 31/74 (2020.01);
U.S. Cl.
CPC ...
G01R 31/2607 (2013.01); G01R 31/74 (2020.01); H01L 22/14 (2013.01); H01L 23/5226 (2013.01); H01L 23/5256 (2013.01); H01L 23/5283 (2013.01); H01L 22/34 (2013.01);
Abstract

A semiconductor wafer includes a semiconductor substrate having a plurality of die areas separated from one another by dicing areas. Each die area includes one or more metal layers above the semiconductor substrate and a plurality of fuse structures formed in at least one of the one or more metal layers. Each fuse structure includes a fuse area between first and second fuse heads. Each die area also includes a first pair of contacts connected to different areas of the first fuse head of at least some of the fuse structures. The wafer can be singulated along the dicing areas into individual dies. A corresponding method of fuse verification is also provided.


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