The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Dec. 20, 2019
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Hem Takiar, Fremont, CA (US);

Michael Mostovoy, San Ramon, CA (US);

Emilio Yero, Sunnyvale, CA (US);

Gokul Kumar, San Jose, CA (US);

Yan Li, Milpitas, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 24/04 (2013.01); H01L 24/09 (2013.01); H01L 24/48 (2013.01); H01L 24/80 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/09515 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/80203 (2013.01); H01L 2224/80205 (2013.01); H01L 2224/80815 (2013.01); H01L 2225/06562 (2013.01);
Abstract

A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.


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