The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2021
Filed:
May. 07, 2019
Google Llc, Mountain View, CA (US);
Nam Hoon Kim, San Jose, CA (US);
Woon Seong Kwon, Cupertino, CA (US);
Teckgyu Kang, Saratoga, CA (US);
Google LLC, Mountain View, CA (US);
Abstract
A packaged assembly and a method of producing the packaged assembly is disclosed. The packaged assembly includes a redistribution layer (RDL), an integrated circuit (IC), one or more memory modules, and an interposer comprising a plurality of vias from a list of through-silicon-vias (TSVs), through-mold-via (TMVs), and plated-through-hold-via (PTHs). In some implementations, the IC is electrically and mechanically attached to a first side of the RDL. In some implementations, the one or more memory modules and the interposer are disposed on a second side of the RDL. The packaged assembly also includes a mold having a mold material encapsulating the IC, the one or more memory modules, the interposer, and the RDL to form the packaged assembly. In some implementations, the IC is electrically conductively connected an external circuit board via a series of electrical connections between the IC, the RDL, the vias, and the external circuit board.