The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Jan. 31, 2019
Applicant:

Murata Manufacturing Co., Ltd., Nagaokakyo, JP;

Inventors:

Terutoki Kasamatsu, Nagaokakyo, JP;

Syuichi Nabekura, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01G 4/228 (2006.01); H01L 49/02 (2006.01); H01G 2/02 (2006.01); H01G 4/005 (2006.01); H01G 4/232 (2006.01); H05K 1/16 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01G 2/02 (2013.01); H01G 4/005 (2013.01); H01G 4/228 (2013.01); H01G 4/232 (2013.01); H01L 28/60 (2013.01); H01L 23/642 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3512 (2013.01); H05K 1/162 (2013.01);
Abstract

In an electronic component, a first ground land and a first hot land are provided on a mounting surface of a first substrate. A semiconductor chip is mounted on a first surface and a first ground land and a first hot land are provided on a second surface of a second substrate, and the second surface faces the mounting surface of the first substrate. A three-terminal capacitor is between the first substrate and second substrates. The first ground land of the first substrate and a first ground electrode of the three-terminal capacitor are connected to each other with a solder bump interposed therebetween, the first hot land of the first substrate and a first hot electrode of the three-terminal capacitor are connected to each other with a solder bump interposed therebetween, the first ground land of the second substrate and a second ground electrode of the three-terminal capacitor are connected to each other with a solder bump interposed therebetween, and the first hot land of the second substrate and a second hot electrode of the three-terminal capacitor are connected to each other with a solder bump interposed therebetween.


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