The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2021

Filed:

Aug. 29, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Yuri Terada, Yokohama Kanagawa, JP;

Noriyasu Kumazaki, Kawasaki Kanagawa, JP;

Yasufumi Kajiyama, Kamakura Kanagawa, JP;

Akio Sugahara, Yokohama Kanagawa, JP;

Masahiro Yoshihara, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/30 (2006.01); G11C 16/32 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G06F 3/06 (2006.01); G01K 3/10 (2006.01); G01K 1/14 (2021.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G01K 1/14 (2013.01); G01K 3/10 (2013.01); G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01);
Abstract

A semiconductor storage device includes a memory cell array, a temperature sensor configured to generate a first temperature signal corresponding to a temperature of the memory cell array in response to a first command periodically generated during a waiting period of the memory cell array, a storage circuit configured to store the first temperature signal and update the first temperature signal each time the first command is generated during the waiting period, and a voltage generation circuit configured to generate a voltage to be applied to the memory cell array based on the first temperature signal stored in the storage circuit.


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