Low-power hardware acceleration method and system for convolution neural network computation

Abstract

A method of processing a layer in a convolutional neural network includes reading a plurality of different subsets of pairs of input vector values and corresponding weight vector values from an on-chip memory, storing the pair values in registers of a plurality of multiplication units, simultaneously processing the different subsets of pairs of values in the registers by multiplying the pairs of values and accumulating the results of the multiplications to obtain an output vector for a current layer. The input vector and the weight vector have floating point values and multiplying the pairs of values comprises adding corresponding pairs of integers in a log domain, and an input value or weight value is released from the on-chip memory after said input value or weight value is no longer needed for calculating non-computed output vector values.