Techniques for pre-silicon testing integrated circuit designs that accommodate power-supply noise and adaptive-clock aware timing

Abstract

Various embodiments of the disclosure disclosed herein provide techniques for pre-silicon testing of a design for an integrated circuit. A pre-silicon testing system identifies one or more critical paths included in the integrated circuit. The pre-silicon testing system performs a based noise simulation to generate one or more voltage waveforms at each gate associated with the one or more critical paths. The pre-silicon testing system applies the one or more voltage waveforms to one or more netlists corresponding to the one or more critical paths to generate one or more modified netlists. The pre-silicon testing system performs a timing analysis on the one or more modified netlists to determine a set of slack times that correspond to a set of voltages applied to the integrated circuit. The pre-silicon testing system determines a first critical path that has a lowest slack time relative to all other critical paths.