The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2021
Filed:
Jun. 13, 2017
Hitachi, Ltd., Tokyo, JP;
Toru Motoya, Tokyo, JP;
Masahiro Shiraishi, Tokyo, JP;
Satoshi Nishikawa, Tokyo, JP;
Keisuke Yamamoto, Tokyo, JP;
Tadanobu Toba, Tokyo, JP;
Takumi Uezono, Tokyo, JP;
Hideo Harada, Tokyo, JP;
Yusuke Kanno, Tokyo, JP;
HITACHI, LTD., Tokyo, JP;
Abstract
A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.