The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

May. 18, 2020
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Xu Zhang, Chandler, AZ (US);

Siamak Delshadpour, Phoenix, AZ (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H03K 17/687 (2006.01); H03K 17/60 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03878 (2013.01); H03K 17/60 (2013.01); H03K 17/687 (2013.01); H04L 25/03012 (2013.01);
Abstract

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes an input port, an output port, a first differential transistor pair coupled to the input port and the output port and a second differential transistor pair. The CTLE circuit further includes a first degenerative impedance circuit coupled between the first differential transistor pair and ground. The first degenerative impedance includes switchable components to vary impedance of the first degenerative impedance circuit. The CTLE circuit also includes a second degenerative impedance circuit coupled between the second differential transistor pair and ground. The second degenerative impedance includes switchable components to vary impedance of the second degenerative impedance circuit, wherein the resistive part of the impedance of the first degenerative impedance circuit is equal to the impedance of the second degenerative impedance circuit.


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