The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2021
Filed:
Oct. 23, 2020
Ningbo University, Zhejiang, CN;
Pengjun Wang, Zhejiang, CN;
Shunxin Ye, Zhejiang, CN;
Yuejun Zhang, Zhejiang, CN;
Huihong Zhang, Zhejiang, CN;
Xiaotian Zhang, Zhejiang, CN;
Ningbo University, Zhejiang, CN;
Abstract
A positive feedback XOR/XNOR gate and a low-delay hybrid logic adder are provided. The low-delay hybrid logic adder comprises the positive feedback XOR/XNOR gate and an output circuit. The positive feedback XOR/XNOR gate comprises a first PMOS transistor and a second PMOS transistor used as pass transistors, a first NMOS transistor and a second NMOS transistor constituting a pull-down network, and a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor constituting a positive feedback loop. When an XOR logic output terminal of the positive feedback XOR/XNOR gate is pulled down below a switching threshold of an inverter formed by the third PMOS transistor and the fourth NMOS transistor, the positive feedback loop starts to operate to enable the XOR logic output terminal of the positive feedback XOR/XNOR gate to enter a pull-down phase to be pulled down to a low level to avoid threshold voltage losses.