The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2021
Filed:
Aug. 06, 2019
Applicants:
SK Hynix Inc., Icheon, KR;
Industry-academic Cooperation Foundation, Yonsei University, Seoul, KR;
Inventors:
Jeongbin Kim, Seoul, KR;
Kitae Kim, Seoul, KR;
Kyungseon Cho, Seoul, KR;
Seungjin Lee, Seoul, KR;
Daehyung Cho, Seoul, KR;
Eui-Young Chung, Seongnam, KR;
Hongil Yoon, Seoul, KR;
Assignees:
SK hynix Inc., Icheon, KR;
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY, Seoul, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/34 (2020.01); H03K 19/17 (2006.01); H03K 19/17728 (2020.01); H03K 19/1776 (2020.01); H03K 19/17736 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17728 (2013.01); G06F 30/34 (2020.01); H03K 19/1776 (2013.01); H03K 19/17736 (2013.01);
Abstract
A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.