The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2021
Filed:
Feb. 20, 2017
City University of Hong Kong, Kowloon, HK;
Quan Xue, Kowloon, HK;
Hao-Tian Zhu, Kowloon, HK;
City University of Hong Kong, Kowloon, HK;
Abstract
Systems and methods which provide low-loss dielectric microstrip line (DML) circuits for use with respect to signals in the terahertz frequency range are described. Low-loss DML integrated circuits of embodiments, such as may comprise DML transmission lines, DML couplers, DML crossovers, etc., may be based on silicon technology and are adapted for signal frequencies in the range of 750-925 GHz. A DML circuit implementation may be comprised of silicon on insulator based DML structure having a silicon dioxide (SiO) insulation layer as the middle layer of the DML, wherein the device layer (HR—Si) and the handle layer (HR—Si) are the top and bottom layers of the DML. A high-precision fabrication process for the SOI wafer, wherein the height of the dielectric microstrip lines can be accurately controlled, may be utilized to fabricate DML circuits of embodiments. A non-contact measurement technology may be used to test the DML circuits of embodiments.