The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Jul. 09, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Yusuke Sakata, Osaka, JP;

Manabu Usuda, Hyogo, JP;

Mitsuyoshi Mori, Kyoto, JP;

Yutaka Hirose, Kyoto, JP;

Yoshihisa Kato, Hyogo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/107 (2006.01); H01L 27/146 (2006.01); H02S 40/44 (2014.01);
U.S. Cl.
CPC ...
H01L 31/1075 (2013.01); H01L 27/1461 (2013.01); H01L 27/1464 (2013.01); H01L 27/14609 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 27/14647 (2013.01); H01L 31/107 (2013.01); H02S 40/44 (2014.12);
Abstract

A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p− type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p− type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p− type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p− type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p− type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.


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