The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Jul. 31, 2018
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Akihiro Hikasa, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 29/0619 (2013.01); H01L 29/0646 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/41708 (2013.01); H01L 29/41766 (2013.01); H01L 29/6634 (2013.01); H01L 29/66348 (2013.01); H01L 29/7395 (2013.01); H01L 29/0649 (2013.01); H01L 29/1095 (2013.01);
Abstract

A semiconductor device is disclosed having a plurality of gate trenches formed on the surface thereof, each filled with a gate insulating film and a gate electrode. A transistor region is defined between adjacent gate trenches forming a pair, and includes an n-type emitter region, a p-type base region, and an n-type drift region disposed lateral to each gate trench in the pair, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer. A p-type collector region disposed on a back surface side of the semiconductor layer with respect to the n-type drift region. A plurality of emitter trenches are formed one either side of each of the gate trenches in the pair of gate trenches.


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