The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Sep. 19, 2018
Applicant:

Denso Corporation, Kariya, JP;

Inventor:

Motoo Yamaguchi, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/739 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/866 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0615 (2013.01); H01L 21/823481 (2013.01); H01L 27/0629 (2013.01); H01L 27/088 (2013.01); H01L 29/0638 (2013.01); H01L 29/404 (2013.01); H01L 29/405 (2013.01); H01L 29/7395 (2013.01); H01L 21/823493 (2013.01); H01L 29/16 (2013.01); H01L 29/78 (2013.01); H01L 29/861 (2013.01); H01L 29/866 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral voltage-withstanding region that are provided on the major surface side of the semiconductor substrate. The element-forming region includes both a cell region for forming a power element and a circuit element region for forming at least one circuit element. The circuit element region is interposed between the outer peripheral voltage-withstanding region and the cell region. The outer peripheral voltage-withstanding region includes a boundary region that adjoins the element-forming region. In the boundary region, there is provided one or more voltage-withstanding regions. At least one of the one or more voltage-withstanding regions has a withstand voltage lower than both the withstand voltages of the cell region and the circuit element region.


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